This invention is directed to an improved phase-locked loop circuit (PLL) that may be used with a synthesizer tuner or the like.
Recently, phase-locked loop circuits (PLL hereafter) have been widely used for synthesizer tuners, etc. However, even when the loop is in a locked state, there is no ideal stable state in the PLL. Thus, phase error voltage is constantly outputted from the phase sensitive detector of the PLL and since it is not completely integrated by the following low-pass filter, some ripple components remain which frequency-modulate the voltge controlled oscillator. This becomes severe when the phase difference between the standard oscillation frequency applied to the phase sensitive detector and the n-divided frequency of the voltage controlled oscillator being compared is large and it deteriorates the performance of the voltage controlled oscillator. In a synthesizer tuner where the size of the phase error voltage depends on the station selected with the receiving band, the S/N fluctuates at each point within the band. Although it is possible to enhance the low pass filter to thereby permit removal of the ripple components, this approach is limited since it causes delayed loop responses and disconnected lock at times.
Further, an improvement in the S/N ratio of a synthesizer tuner may be effected by narrowing the capture range of the PLL circuit low-pass filter. However, when the phase error voltage of the phase sensitive detector of PLL circuit changes, there is a risk that the lock may come off due to the narrow capture range.